1. Field of the Invention
The present invention relates generally to methods for forming patterned thermally extrudable material layers within microelectronic fabrications. More particularly, the present invention relates to planarizing methods for forming patterned thermally extrudable material layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronic fabrication to employ when fabricating patterned microelectronic conductor layers within microelectronic fabrications copper containing conductor materials, in place of more conventional aluminum containing conductor materials.
Copper containing conductor materials are desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers within microelectronic fabrications, in place of more conventional aluminum containing conductor materials for forming patterned microelectronic conductor layers within microelectronic fabrications, insofar as patterned microelectronic conductor layers formed of copper containing conductor materials are generally less susceptible to detrimental effects, such as but not limited to detrimental electromigration effects.
While patterned microelectronic conductor layers formed of copper containing conductor materials are thus clearly desirable in the art of microelectronic fabrication, patterned microelectronic conductor layers formed of copper containing conductor materials are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, it is known in the art of microelectronic fabrication that patterned microelectronic conductor layers formed of copper containing conductor materials are often difficult to form within microelectronic fabrications with enhanced integrity, and in particular with enhanced physical integrity, such as but not limited to enhanced dimensional integrity.
It is thus desirable in the art of microelectronic fabrication to provide methods for forming within microelectronic fabrications, with enhanced integrity, patterned microelectronic conductor layers formed of copper containing conductor materials.
It is towards the foregoing object that the present invention is more specifically directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming, with desirable properties within microelectronic fabrications, patterned microelectronic conductor layers formed of copper containing conductor materials.
For example, McTeer, in U.S. Pat. No. 5,939,788, discloses a plurality of methods for forming, with enhanced manufacturing efficiency, patterned copper containing microelectronic conductor layers within apertures within substrates employed within microelectronic fabrications. To realize the foregoing result, a first representative method within the plurality of methods employs within a microelectronic fabrication a titanium aluminum nitride layer as a thermally stable barrier layer with respect to a patterned copper containing microelectronic conductor layer which is reflowed thereupon within the microelectronic fabrication. Similarly, and also to realize the foregoing object, a second representative method within the plurality of methods employs within a microelectronic fabrication an aluminum layer interposed between a barrier layer and a patterned copper containing microelectronic conductor layer such as to provide for a lowered reflow temperature of the patterned copper containing microelectronic conductor layer within the microelectronic fabrication.
In addition, Nogami et al., in U.S. Pat. No. 6,043,153, discloses a method for forming, with enhanced electromigration resistance, a patterned copper containing microelectronic conductor layer within an aperture within a substrate employed within a microelectronic fabrication. To realize the foregoing object, the method provides that there is first formed a blanket copper containing microelectronic conductor layer covering the substrate employed within the microelectronic fabrication and filling the aperture, and then planarized the blanket copper containing microelectronic conductor layer to form a patterned copper containing microelectronic conductor layer within the aperture, further wherein the patterned copper containing microelectronic conductor layer within the aperture is thermally annealed to form a thermally annealed patterned copper containing microelectronic conductor layer within the aperture prior to forming thereover a passivation layer.
Desirable in the art of microelectronic fabrication are additional methods which may be employed for forming within microelectronic fabrications, with enhanced integrity, patterned microelectronic conductor layers formed of copper containing conductor materials.
It is towards the foregoing object that the present invention is more specifically directed.
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a patterned copper containing microelectronic conductor layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the patterned copper containing microelectronic conductor layer is formed with enhanced integrity.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a patterned microelectronic layer within a microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate having an aperture formed therein. There is then formed over the substrate and filling the aperture a blanket microelectronic layer. There is then planarized, while employing a first planarizing method, the blanket microelectronic layer to form a once planarized patterned microelectronic layer within the aperture. There is then thermally annealed, while employing a thermal annealing method, the once planarized patterned microelectronic layer within the aperture to form a thermal annealed once planarized patterned microelectronic layer within the aperture. Finally, there is then planarized, while employing a second planarizing method, the thermal annealed once planarized patterned microelectronic layer within the aperture to form a thermal annealed twice planarized patterned microelectronic layer within the aperture.
Within the present invention, when the blanket microelectronic layer is formed of a thermally extrudable material in general, such as but not limited to a thermally extrudable copper containing conductor material more particularly, the thermal annealed twice planarized patterned microelectronic layer, such as a thermal annealed twice planarized patterned copper containing conductor layer, is formed with enhanced integrity, and in particular enhanced physical integrity, such as but not limited to enhanced dimensional integrity.
The present invention provides a method for forming within a microelectronic fabrication a patterned copper containing microelectronic conductor layer, wherein the patterned copper containing microelectronic conductor layer is formed with enhanced integrity.
The present invention realizes the foregoing object by employing a two step planarizing method for forming within an aperture within a substrate employed within a microelectronic fabrication a planarized patterned copper containing conductor layer, further wherein within the two step planarizing method there is employed interposed between a pair of planarizing process steps which comprises the two step planarizing method a thermal annealing process step which also comprises the two step planarizing method.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication but employed within the context of a specific process ordering and specific series of process limitations to provide the present invention. Since it is thus at least in part a specific process ordering and a specific series of process limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.